1. Field of the Invention
The present invention relates to a manufacturing method of a gate-split flash memory, and particularly to a manufacturing method of a gate-split flash memory which can remove unnecessary peaks in a floating gate polysilicon region.
2. Description of Related Art
For a prior art manufacturing method of a flash memory, a source region of the flash memory is manufactured by a similar resist-stripping way. Therefore, if there is a demand to reduce the size of the flash memory, a STI technology is always used, which separates the source region into several parts and connecting them by a plurality of local wires. A disadvantage of the STI technology is incompatible with the process of the modern gate-split flash memory. A prior art method which increases a barrier oxide layer to generate a self-aligned salicide floating memory will cause unequal gate lengths and bad removal rate. Generally speaking, if a misalignment happens in defining the floating gate by a pattern of a mask, the channel length and operational characteristic of the flash memory will be heavily affected. Several prior arts, which disclose how to avoid misalignment of a split control gate, can be found in U.S. Pat. Nos. 5,278,087 and 5,940,706. Meanwhile, the prior art also discloses another method of utilizing a spacer to define a floating gate and avoid asymmetric situations when utilizing a mask.
FIGS. 1(a)-(j) shows a prior art manufacturing flow of the flash memory using a self-align contact process. In FIG. 1(a), a flash memory 10 includes a substrate (such as a P-type carrier) 101, a tunnel dielectric layer 102, a first polysilicon 103 acting as a floating gate, a silicon nitride layer (such as Si4N4) 104 and a resist 105 acting as a channel mask. The resist 105 has an opening 120 for forming the region of the floating gate. In FIG. 1(b), the silicon nitride layer 104 corresponding to the opening 120 is etched. In FIG. 1(c), a polysilicon-oxide region 106 is formed by thermal oxidation, and is represented by a cross section of an ellipse. FIG. 1(d) is a cross-sectional view taken from another direction. In FIG. 1(e), the polysilicon-oxide region 106 is used as a hard mask, that used in removing all polysilicon except that under the polysilicon-oxide region 106 forming a separate floating gate, which is called xe2x80x9cfloating gate polysiliconxe2x80x9d 117. In FIG. 1(f), a polysilicon layer 111 acts as a control gate, on which a W-silicide layer 107 (such as WsiX) and a silicon nitride layer 108 (such as a cap SiN) are deposited in order. Two peaks 115 and 116 are formed on two sides of the top surface of the floating gate polysilicon 117. Generally speaking, a field emission functions as one method to erase data stored in a non-volatilc memory, and has been largely used. When the function of the field emission is utilized, peaks on the floating gate must be generated first. However, only below the control gate, the peak can develop the function of field emission, and peaks on the other places not only fail to develop the function of field emission, but also affect an yield of the salicide process. For example, in FIG. 1(f), the peak 115 beneath the control gate 111 can erase the data of the flash memory by utilizing the function of field emission, but the peak 116 has not the function and is an invalid one. In FIG. 1(g), after an annealing process, a NLDD region 110 and N+ region 109 are formed by an ion implantation process. In FIG. 1(h), a spacer dielectric 112 is deposited, and a spacer etching is executed, and the invalid peak 116 would be exposed, causing a short circuit or a current leakage between the polysilicon-oxide region and source region. In FIG. 1(i), a barrier layer 113 is deposited to prevent contacts inside the flash memory from being etched. In FIG. 1(j), an inter-layer-dielectric (ILD) 114 is deposited and oxide in the source region is removed.
FIGS. 2(a)-(d) shows another prior art manufacturing flow of the flash memory using a fully salicide-compatible process. The first flows of the manufacturing method of the an other prior art is the same as those shown in FIGS. 1(a)-(e). In FIG. 2(a), a polysilicon layer 111 is deposited In FIG. 2(b), an annealing process is first executed, and a NLDD region 110 and N+ region 109 are formed by an ion implantation process. In FIG. 2(c), a spacer dielectric 112 is deposited, a spacer etching is executed, and the invalid peak 116 will be exposed, causing the floating gate to be salicided. In FIG. 2(d), for a stand-alone memory process, W-silicide is utilized as the material of a third polysilicon layer 118; for an embedded memory process, Ti-silicide is used as the material of the third polysilicon layer 118.
In conclusion, the peaks only beneath the control gate have the ability of erasing data stored in the flash memory, and peaks on the other positions do not have the ability and lead to a short circuit, current leakage or being salicided, because they are exposed outside the control gate after a spacer etching is executed. Besides, when the oxide in the source region is etched, the oxide in the floating gate will be also etched. In this circumstance, if the contacts inside the flash memory are etched, the channel length between the source region and floating gate will be shortened and an error will happen.
A first object of the present invention is to eliminate the disadvantage of generating invalid peaks in the prior art manufacturing process of a gate-split flash memory. The present invention masks the invalid peaks with a thick passivation layer to obtain the purpose of removing the invalid peaks in the manufacturing process of the flash memory. The present invention is suitable to two main processes for the gate-split flash memory. The two processes are self-align contact process and fully-salicide-compatible process.
A second object of the present invention is to propose a manufacturing method of keeping a complete channel length of the flash memory. In the self-align contact process, the present invention deposits a nitride spacer to define a pattern of the floating gate of the flash memory, so that the channel length of the floating gate can be finely defined. In the fully-salicide-compatible process, the present invention utilizes a mask pattern to define the floating gate region of the flash memory, and the manufacturing process will be smooth and cheap.